A conventional source synchronous clocking architecture can be used in, for example, memory systems to provide a reference clock to one or more dynamic random access memory (DRAM) devices. In conventional source synchronous systems, a memory controller generates the reference clock using, for example, a phase locked loop. The memory controller then provides the reference clock to a primary DRAM which, in turn, distributes the reference clock to the receiver clock trees of one or more secondary DRAMs.
The primary DRAM receives the reference clock and propagates it through a receiver clocking tree and a transmitter clocking tree. The reference clock then passes through the receiver clock tree of a secondary DRAM. Each secondary DRAM uses the reference clock to control the transmission of data back to the primary DRAM. In general, the reference clock used to control the transmission of data back to the primary DRAM has traversed the memory controller clock tree, the channel, the primary DRAM receiver clock tree and the primary DRAM transmitter clock tree.
The clock cycle receiving the data at the primary DRAM will be a few cycles different from the one transmitting it at the secondary DRAM. In the presence of supply noise in the range of (for example) 100 Mhz or greater, this clock to data delay mismatch results in significant jitter. The jitter can make the reference clock unusable above certain frequencies for many applications.